The technology relates generally to a technology of controlling an information processing device, and more particularly to an instruction processing technology.
An information processing device adopting a highly advanced instruction processing system after adopting a pipeline processing system, has schemed to improve the performance by speculatively processing a subsequent instruction without waiting for an end of executing one instruction. As a matter of course, the performance has been improved by speculatively supplying the instructions (fetching the instructions) in advance of executing the instructions. Herein, the term “speculative” connotes, e.g., fetching the subsequent instruction from the branch target address according to a predetermined prediction result before the fetch address of the subsequent instruction is determined, and processing the subsequent instruction.
In the instruction buffer system, the speculatively-fetched instruction is temporarily retained in an instruction buffer. Then, the instruction buffer supplies the instructions to an execution control unit which interprets and executes the instruction. The speculative fetch can be advanced forward by having this type of plural instruction buffers. Resources of the information processing device are not, however, limitless, and therefore an endeavor was such that the instruction buffers are utilized efficiently by, for instance, a method disclosed in Patent document 1.    [Patent document 1] Japanese Patent Publication No. 3845043    [Patent document 2] Japanese Patent Publication No. 3683968